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2:1 HDMI/DVI Switch with Equalization and DDC/CEC Buffers AD8192
FEATURES
2 inputs, 1 output HDMI/DVI links HDMI 1.3a receive and transmit compliant 7 kV HBM ESD on HDMI input pins 4 TMDS channels per link Supports 250 Mbps to 2.25 Gbps data rates and beyond Supports 25 MHz to 225 MHz pixel clocks and beyond Fully buffered unidirectional inputs/outputs Switchable 50 on-chip input terminations with programmable or automatic control on channel switch Equalized inputs and pre-emphasized outputs Low added jitter Output disable feature for reduced power dissipation Switched output termination for building of larger arrays Bidirectional and cascadable DDC buffers (SDA/SCL) DDC bus logic level translation (3.3 V, 5 V) Bidirectional and cascadable CEC buffer with integrated pull-up resistors (27 k) Hot plug detect pulse low on channel switch Standards compatible: DVI, HDMI 1.3a, HDCP, I2C Serial (I2C slave) control interface 56-lead, 8 mm x 8 mm LFCSP, RoHS-compliant package
I2C_SDA I2C_SCL I2C_ADDR
FUNCTIONAL BLOCK DIAGRAM
RESET SERIAL INTERFACE CONFIG INTERFACE CONTROL LOGIC
AD8192
AVCC DVCC AMUXVCC AVEE DVEE VREF_AB VREF_COM
VTTI + - + - 2 2 SWITCH CORE 2 DDC_COM[1:0] DVEE 4 4 4 4 HIGH SPEED BUFFERED EQ SWITCH CORE 4 PE 4 + - VTTO
IP_A[3:0] IN_A[3:0]
OP[3:0] ON[3:0]
IP_B[3:0] IN_B[3:0]
VTTI DDC_A[1:0] DDC_B[1:0]
CEC_I/O HPD_A HPD_B LOW SPEED BUFFERED
CEC_O/I
Figure 1.
TYPICAL APPLICATION APPLICATIONS
Front panel buffer for advanced television (HDTV) sets Standalone HDMI switcher Multiple input displays Projectors A/V receivers Set-top boxes
SET-TOP BOX HDTV SET HDMI RECEIVER DVD PLAYER
07050-002
AD8192
Figure 2. Typical Application for HDTV Sets
GENERAL DESCRIPTION
The AD8192 is a complete HDMITM/DVI link switch featuring equalized TMDS inputs and pre-emphasized TMDS outputs ideal for systems with long cable runs. The TMDS outputs can be set to a high impedance state to reduce the power dissipation and/or allow the construction of larger arrays using the wireOR technique. The AD8192 includes bidirectional buffering for the DDC bus and CEC line, with integrated pull-up resistors for the CEC line. The AD8192 is available in a space-saving, 56-lead LFCSP surface-mount, lead-free plastic package specified to operate over the -40C to +85C temperature range.
PRODUCT HIGHLIGHTS
1. 2. Fully HDMI 1.3a transmit and receive compliant. Supports data rates up to 2.25 Gbps, enabling greater than 1080p HDMI formats with deep color (12-bit) and UXGA (1600 x 1200) DVI resolutions. Input cable equalizer enables use of long cables; more than 20 m (24 AWG) at data rates up to 2.25 Gbps. Auxiliary switch isolates and buffers the DDC bus and the CEC line, improving total system capacitance limit. Hot plug detect (HPD) signal is pulsed low on link switch. Manually or automatically switched input terminations.
3. 4. 5. 6.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
07050-001
BIDIRECTIONAL
AD8192 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Typical Application........................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 12 Input Channels............................................................................ 12 Output Channels ........................................................................ 12 Switching Mode .......................................................................... 13 Pre-Emphasis .............................................................................. 13 Auxiliary Multiplexer ................................................................. 14 DDC Logic Levels....................................................................... 14 Input/Output Mapping Control ............................................... 14 Serial Control Interface.................................................................. 15 Reset ............................................................................................. 15 Write Procedure.......................................................................... 15 Read Procedure........................................................................... 16 Configuration Registers ................................................................. 17 High Speed Device Modes Register ......................................... 18 Auxiliary Device Modes Register ............................................. 18 Receiver Settings Register ......................................................... 18 Input Termination Control Register ........................................ 18 Receive Equalizer Register ........................................................ 18 Transmitter Settings Register .................................................... 19 Source Sign Control Register .................................................... 19 Source A Input/Output Mapping Register.............................. 19 Source B Input/Output Mapping Register .............................. 19 Applications Information .............................................................. 20 Pinout ........................................................................................... 20 Cable Lengths and Equalization ............................................... 21 TMDS Output Rise/Fall Times ................................................. 21 Front Panel Buffer for Advanced TV....................................... 21 HDMI Switcher .......................................................................... 21 Cascading Multiple Devices...................................................... 21 PCB Layout Guidelines.............................................................. 22 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 25
REVISION HISTORY
5/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD8192 SPECIFICATIONS
TA = 27C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, VREF_AB = 5 V, VREF_COM = 5 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, TMDS outputs terminated with external 50 resistors to 3.3 V, unless otherwise noted. Table 1. TMDS Performance Specifications
Parameter TMDS DYNAMIC PERFORMANCE Maximum Data Rate (DR) per Channel Bit Error Rate (BER) Added Data Jitter Added Clock Jitter Differential Intrapair Skew Differential Interpair Skew TMDS EQUALIZATION PERFORMANCE Receiver (Highest Setting) 1 Transmitter (Highest Setting) 2 TMDS INPUT CHARACTERISTICS Input Voltage Swing Input Common-Mode Voltage (VICM) TMDS OUTPUT CHARACTERISTICS High Voltage Level Low Voltage Level Rise/Fall Time (20% to 80%) 3 TMDS TERMINATION Input Termination Resistance Output Termination Resistance
1 2
Conditions/Comments NRZ PRBS 223 - 1 DR 2.25 Gbps, PRBS 27 - 1, no equalization At output At output Boost frequency = 1.125 GHz Boost frequency = 1.125 GHz Differential
Min 2.25
Typ
Max
Unit Gbps
10-9 23 1 1 30 12 6 150 AVCC - 800 AVCC - 200 AVCC - 600 50 1200 AVCC AVCC + 10 AVCC - 400 150 ps (p-p) ps (rms) ps ps dB dB mV mV mV mV ps
Single-ended high speed channel Single-ended high speed channel DR = 2.25 Gbps Single-ended Single-ended
90 50 50
Output meets transmitter eye diagram as defined in the DVI Standard Revision 1.0 and HDMI Standard Revision 1.3a. Cable output meets receiver eye diagram mask as defined in the DVI Standard Revision 1.0 and HDMI Standard Revision 1.3a. 3 Output rise/fall time measurement excludes external components such as HDMI connector or external ESD protection diodes. See Applications Information section for more information.
Table 2. Auxiliary Channel Performance Specifications
Parameter DDC CHANNELS Input Capacitance Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Rise Time Fall Time Leakage CEC CHANNEL Input Capacitance Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage, VOH Symbol CAUX VIL VIH VOL VOH Conditions/Comments DC bias = 2.5 V, ac voltage = 3.5 V p-p, f = 100 kHz 0.7 x VREF 1 IOL = 5 mA 10% to 90%, no capacitive load 90% to 10%, CLOAD = 400 pF VREF1 140 100 0.4 Min Typ 10 Max 15 0.5 Unit pF V V V V ns ns A pF V V V V
200 10 25 0.8 0.6
CAUX VIL VIH VOL
DC bias = 1.65 V, ac voltage = 2.5 V p-p, f = 100 kHz 2.0 RPULLUP = 3 k to +3.3 V 2.5
5
AVCC
Rev. 0 | Page 3 of 28
AD8192
Parameter Rise Time Fall Time Leakage HOT PLUG DETECT Output Low Voltage
1
Symbol
Conditions/Comments 10% to 90%, CLOAD = 1500 pF, RPULLUP = 27 k; or CLOAD = 7200 pF, RPULLUP = 3 k 90% to 10%, CLOAD = 1500 pF, RPULLUP = 27 k; or CLOAD = 7200 pF, RPULLUP = 3 k Off-leakage test conditions from HDMI Compliance Test Specification Test ID: 8-14 RPULLUP = 800 to +5 V
Min
Typ 50 5
Max 100 10 1.8
Unit s s A
VOL
0.4
V
VREF refers to the voltage at the VREF_AB or VREF_COM pins. VREF should be at the same supply voltage as that to which the external pull-up resistors are connected.
Table 3. Power Supply and Control Logic Specifications
Parameter POWER SUPPLY AVCC AMUXVCC VREF_AB VREF_COM QUIESCENT CURRENT AVCC AVCC AVCC VTTI VTTO DVCC VREF_AB VREF_COM AMUXVCC POWER DISSIPATION Outputs disabled Outputs enabled, no pre-emphasis Outputs enabled, maximum pre-emphasis I2C(R) AND LOGIC INPUTS 2 Input High Voltage, VIH Input Low Voltage, VIL I2C AND LOGIC OUTPUTS Output Low Voltage, VOL
1 2
Conditions/Comments Operating range (3.3 V 5%) Operating range (5 V 10%)
Min 3.135 4.5 3 3
Typ 3.3 5 5 5 40 60 100 40 40 80 10 1 1 10 215 545 881
Max 3.465 5.5 5.5 5.5 45 70 120 54 50 100 15 10 10 20 318 765 1200
Unit V V V V mA mA mA mA mA mA mA A A mA mW mW mW V V V
Outputs disabled Outputs enabled, no pre-emphasis Outputs enabled, maximum pre-emphasis Input termination on 1 Outputs enabled, output termination on Output termination on, maximum pre-emphasis
Serial interface Serial interface Serial interface, IOL = +3 mA
2.4 0.8 0.4
Assumes that the unselected HDMI/DVI link is deactivated through the hot plug detect line, as required by the DVI Standard Revision 1.0 and HDMI Standard Revision 1.3a. The AD8192 is an I2C slave and its control interface is based on the 3.3 V I2C bus specification.
Rev. 0 | Page 4 of 28
AD8192 ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter AVCC to AVEE DVCC to DVEE DVEE to AVEE VTTI VTTO AMUXVCC VREF_AB VREF_COM Internal Power Dissipation High Speed Input Voltage High Speed Differential Input Voltage Low Speed Input Voltage I2C Logic Input Voltage Storage Temperature Range Operating Temperature Range Junction Temperature ESD HBM Input Pins Only ESD HBM All Other Pins Rating 3.7 V 3.7 V 0.3 V AVCC + 0.6 V AVCC + 0.6 V 5.5 V 5.5 V 5.5 V 2.41 W AVCC - 1.4 V < VIN < AVCC + 0.6 V 2.0 V DVEE - 0.3 V < VIN < AMUXVCC + 0.6 V DVEE - 0.3 V < VIN < DVCC + 0.6 V -65C to +125C -40C to +85C 150C 7 kV 1.5 kV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a four-layer JEDEC circuit board for surface-mount packages. JC is specified for the exposed pad soldered to the circuit board with no airflow. Table 5. Thermal Resistance
Model 56-Lead LFCSP JA 27 JC 2.1 Unit C/W
ESD CAUTION
Rev. 0 | Page 5 of 28
AD8192 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
56 55 54 53 52 51 50 49 48 47 46 45 44 43
AVCC IN_A0 IP_A0 AVEE IN_A1 IP_A1 VTTI IN_A2 IP_A2 AVCC IN_A3 IP_A3 AVEE I2C_ADDR
DDC_A0 DDC_A1 HPD_A CEC_I/O DVEE VREF_AB DDC_COM0 DDC_COM1 VREF_COM AMUXVCC CEC_O/I DDC_B0 DDC_B1 HPD_B
PIN 1 INDICATOR
1 2 3 4 5 6 7 8 9 10 11 12 13 14
AD8192
TOP VIEW (Not to Scale)
42 41 40 39 38 37 36 35 34 33 32 31 30 29
AVCC IP_B3 IN_B3 AVEE IP_B2 IN_B2 VTTI IP_B1 IN_B1 AVCC IP_B0 IN_B0 AVEE I2C_SDA
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 1, 10, 33, 42 2 3 4, 13, 30, 39, ePAD 5 6 7, 36 8 9 11 12 14 15, 21 16 17 18, 24 19 20 22 23 25 26 27 28 29 31 32 34 35 Mnemonic AVCC IN_A0 IP_A0 AVEE IN_A1 IP_A1 VTTI IN_A2 IP_A2 IN_A3 IP_A3 I2C_ADDR DVCC ON0 OP0 VTTO ON1 OP1 ON2 OP2 ON3 OP3 RESET I2C_SCL I2C_SDA IN_B0 IP_B0 IN_B1 IP_B1 Type 1 Power HS I/O HS I/O Power HS I/O HS I/O Power HS I/O HS I/O HS I/O HS I/O Control Power HS I/O HS I/O Power HS I/O HS I/O HS I/O HS I/O HS I/O HS I/O Control Control Control HS I/O HS I/O HS I/O HS I/O Description Positive Analog Supply. 3.3 V nominal. High Speed Input Complement. High Speed Input. Negative Analog Supply. 0 V nominal. High Speed Input Complement. High Speed Input. Input Termination Supply. Nominally connected to AVCC. High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input. I2C Address LSB. Positive Digital Power Supply. 3.3 V nominal. High Speed Output Complement. High Speed Output. Output Termination Supply. Nominally connected to AVCC. High Speed Output Complement. High Speed Output. High Speed Output Complement. High Speed Output. High Speed Output Complement. High Speed Output. Configuration Registers Reset. Normally pulled to AVCC. I2C Clock. I2C Data. High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input.
Rev. 0 | Page 6 of 28
07050-003
NOTES 1. THE AD8192 LFCSP HAS AN EXPOSED PADDLE (ePAD) ON THE UNDERSIDE OF THE PACKAGE WHICH AIDS IN HEAT DISSIPATION. THE ePAD MUST BE ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE IN ORDER TO MEET THERMAL SPECIFICATIONS.
DVCC ON0 OP0 VTTO ON1 OP1 DVCC ON2 OP2 VTTO ON3 OP3 RESET I2C_SCL
15 16 17 18 19 20 21 22 23 24 25 26 27 28
AD8192
Pin No. 37 38 40 41 43 44 45 46 47 48 49 50 51 52 53 54 55 56
1
Mnemonic IN_B2 IP_B2 IN_B3 IP_B3 HPD_B DDC_B1 DDC_B0 CEC_O/I AMUXVCC VREF_COM DDC_COM1 DDC_COM0 VREF_AB DVEE CEC_I/O HPD_A DDC_A1 DDC_A0
Type 1 HS I/O HS I/O HS I/O HS I/O LS O LS I/O LS I/O LS I/O Power Reference LS I/O LS I/O Reference Power LS I/O LS O LS I/O LS I/O
Description High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input. Hot Plug Detect Output. Display Data Channel Input/Output. Display Data Channel Input/Output. Consumer Electronics Control Output/Input. Positive Auxiliary Switch Supply. 5 V typical. Positive Auxiliary Switch Supply Common Side. Display Data Channel Common Input/Output. Display Data Channel Common Input/Output. Positive Auxiliary Switch Supply Source Side. Negative Digital and Auxiliary Switch Power Supply. 0 V nominal. Consumer Electronics Control Input/Output. Hot Plug Detect Output. Display Data Channel Input/Output. Display Data Channel Input/Output.
HS = high speed, LS = low speed, I = input, O = output.
Rev. 0 | Page 7 of 28
AD8192 TYPICAL PERFORMANCE CHARACTERISTICS
TA = 27C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 - 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 resistors to 3.3 V, unless otherwise noted.
HDMI CABLE DIGITAL PATTERN GENERATOR
EVALUATION BOARD
AD8192
SERIAL DATA ANALYZER
SMA COAX CABLE
07050-004
REFERENCE EYE DIAGRAM AT TP1
TP1
TP2
TP3
Figure 4. Test Circuit Diagram for Rx Eye Diagrams
250mV/DIV
07050-005
250mV/DIV
0.125UI/DIV AT 2.25Gbps
0.125UI/DIV AT 2.25Gbps
Figure 5. Rx Eye Diagram at TP2 (Cable = 2 m, 30 AWG)
Figure 7. Rx Eye Diagram at TP3, EQ = 12 dB (Cable = 2 m, 30 AWG)
250mV/DIV
250mV/DIV
07050-006
0.125UI/DIV AT 2.25Gbps
0.125UI/DIV AT 2.25Gbps
Figure 6. Rx Eye Diagram at TP2 (Cable = 20 m, 24 AWG)
Figure 8. Rx Eye Diagram at TP3, EQ = 12 dB (Cable = 20 m, 24 AWG)
Rev. 0 | Page 8 of 28
07050-008
07050-007
AD8192
TA = 27C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 - 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 resistors to 3.3 V, unless otherwise noted.
HDMI CABLE DIGITAL PATTERN GENERATOR
EVALUATION BOARD
AD8192
SERIAL DATA ANALYZER
SMA COAX CABLE
07050-009
REFERENCE EYE DIAGRAM AT TP1
TP1
TP2
TP3
Figure 9. Test Circuit Diagram for Tx Eye Diagrams
250mV/DIV
07050-010
250mV/DIV
0.125UI/DIV AT 2.25Gbps
0.125UI/DIV AT 2.25Gbps
Figure 10. Tx Eye Diagram at TP2, PE = 0 dB
Figure 12. Tx Eye Diagram at TP3, PE = 0 dB (Cable = 2 m, 24 AWG)
250mV/DIV
250mV/DIV
07050-011
0.125UI/DIV AT 2.25Gbps
0.125UI/DIV AT 2.25Gbps
Figure 11. Tx Eye Diagram at TP2, PE = 6 dB
Figure 13. Tx Eye Diagram at TP3, PE = 6 dB (Cable = 10 m, 24 AWG)
Rev. 0 | Page 9 of 28
07050-013
07050-012
AD8192
TA = 27C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 - 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 resistors to 3.3 V, unless otherwise noted.
0.6 0.6 ALL CABLES = 24 AWG, EQ = 12dB 0.5 0.5
DETERMINISTIC JITTER (UI)
0.4
DETERMINISTIC JITTER (UI)
0.4 2.25Gbps, PE OFF 0.3 1.5Gbps, PE OFF 0.2 0.75Gbps, MAX PE 0.1
07050-017
0.3 2.25Gbps, EQ = 12dB 0.2
0.75Gbps, PE OFF 2.25Gbps, MAX PE 1.5Gbps, MAX PE
1.5Gbps, EQ = 12dB 0.75Gbps, EQ = 12dB
0.1 ALL CABLES = 24 AWG 0 0 5 10 15 20 25 30 35
07050-014
0
0
10
20
30
CABLE LENGTH (m)
HDMI CABLE LENGTH (m)
Figure 14. Jitter vs. Input Cable Length (See Figure 4 for Test Setup)
Figure 17. Jitter vs. Output Cable Length (See Figure 9 for Test Setup)
50 45 40 35 JITTER (ps) 30 25 20 15 10
07050-015
1.2 DJ, EQ = 12dB RJ, EQ = 12dB 1.0
EYE HEIGHT (V)
0.8
0.6
0.4
0.2
07050-018
5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
2.4
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0 2.2
2.4
DATA RATE (Gbps)
DATA RATE (Gbps)
Figure 15. Jitter vs. Data Rate
Figure 18. Eye Height vs. Data Rate
50 DJ, EQ = 12dB RJ, EQ = 12dB 40
1.2
1.0
JITTER (ps)
30
EYE HEIGHT (V)
07050-016
0.8
0.6
20
0.4
10
0.2
07050-019
0 3.135
3.185
3.235
3.285
3.335
3.385
3.435
0 3.135
3.185
3.235
3.285
3.335
3.385
3.435
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 16. Jitter vs. Supply Voltage
Figure 19. Eye Height vs. Supply Voltage
Rev. 0 | Page 10 of 28
AD8192
TA = 27C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 - 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 resistors to 3.3 V, unless otherwise noted.
50 DJ, EQ = 12dB RJ, EQ = 12dB 40
50 45 40 35 DJ, EQ = 12dB RJ, EQ = 12dB
JITTER (ps)
JITTER (ps)
30
30 25 20 15
20
10
07050-020
10 5 0 2.5 2.7 2.9 3.1 3.3 3.5
07050-023
0
0
0.5
1.0 DIFFERENTIAL SWING (V)
1.5
2.0
3.7
INPUT COMMON-MODE VOLTAGE (V)
Figure 20. Jitter vs. Differential Input Swing
50 DJ, EQ = 12dB RJ, EQ = 12dB 40
100 90 80 70
Figure 23. Jitter vs. Input Common-Mode Voltage
JITTER (ps)
30
RESISTANCE ()
60 OUTPUT 50 40 30 INPUT
20
10
07050-021
20 10 0 -40 -20 0 20 40 60 80
07050-024
0 -40
-20
0
20
40
60
80
TEMPERATURE (C)
TEMPERATURE (C)
Figure 21. Jitter vs. Temperature
120
Figure 24. Single-Ended Termination Resistance vs. Temperature
RISE/FALL TIME 20% TO 80% (ps)
100
80 RISE FALL
60
40
20
07050-022
0 -40
-20
0
20
40
60
80
TEMPERATURE (C)
Figure 22. Rise and Fall Time vs. Temperature
Rev. 0 | Page 11 of 28
AD8192 THEORY OF OPERATION
The primary function of the AD8192 is to switch one of two (HDMI or DVI) single link sources to one output. Each HDMI/DVI link consists of four differential, high speed channels and four auxiliary single-ended, low speed control signals. The high speed channels include a data-word clock and three transition minimized differential signaling (TMDS) data channels running at 10x the data-word clock frequency for data rates up to 2.25 Gbps. The low speed control signals include the display data channel (DDC) bus (SDA and SCL), the consumer electronics control (CEC) line, and the hot plug detect (HPD) signal. All four high speed TMDS channels are identical; that is, the pixel clock can be run on any of the four TMDS channels. Transmit and receive channel compensation is provided for the high speed channels where the user can (manually) select among a number of fixed settings. The AD8192 isolates and buffers the DDC bus. It additionally isolates and buffers the CEC line and includes integrated pullups for the CEC line. The AD8192 also pulses the HPD signal low upon channel switching. The AD8192 has I2C serial programming with two user programmable I2C slave addresses. The I2C slave address of the AD8192 is 0b100100X. The least significant bit, represented by X in the address, is set by tying the I2C_ADDR pin to either 3.3 V (for the value X = 1) or to 0 V (for X = 0).
OP
VTTI 50 50
IP IN
CABLE EQ
AVEE
Figure 25. High Speed Input Simplified Schematic
OUTPUT CHANNELS
Each high speed output differential pair is terminated to the +3.3 V VTTO power supply through a pair of 50 on-chip resistors, as shown in Figure 26. This termination is userselectable; it can be turned on or off by programming the TX_PTO bit of the transmitter settings register.
VTTO
50
50
ON
ESD PROT.
AVEE
INPUT CHANNELS
Each high speed input differential pair terminates to the 3.3 V VTTI power supply through a pair of single-ended 50 onchip resistors, as shown in Figure 25. The state of the input terminations can be configured automatically or programmed manually through the serial control interface. The termination state is placed in the automatic mode by programming 0 in the RX_TO bit of the receiver settings register. In the automatic mode, the selected input has all terminations enabled, and the deselected input has all input terminations disabled. This state is automatically updated upon channel switching. In the manual mode, 1 is programmed into the RX_TO bit of the receiver settings register, and the state of each individual input termination is set by programming the associated RX_PT bits in the input termination control register. The input equalizer can be manually configured to provide two different levels of high frequency boost: 6 dB or 12 dB. The equalizer level defaults to 12 dB after reset. The user can individually program the equalization level of the eight high speed input channels by selectively setting the associated RX_EQ bits in the receive equalizer register. No specific cable length is suggested for a particular equalization setting because cable performance varies widely among manufacturers; however, in general, the equalization of the AD8192 can be set to 12 dB without degrading the signal integrity, even for short input cables.
Figure 26. High Speed Output Simplified Schematic
The output termination resistors of the AD8192 back terminate the output TMDS transmission lines. These back terminations, as recommended in the HDMI 1.3a specification, act to absorb reflections from impedance discontinuities on the output traces, improving the signal integrity of the output traces and adding flexibility to how the output traces can be routed. For example, interlayer vias can be used to route the AD8192 TMDS outputs on multiple layers of the PCB without severely degrading the quality of the output signal. The output has a disable feature that places the outputs in tristate mode (HS_EN bit of the high speed device modes register). Bigger wire-OR'ed arrays can be constructed using the AD8192 in this mode. The AD8192 requires output termination resistors when the high speed outputs are enabled. Termination can be internal and/or external. The internal terminations of the AD8192 are enabled by programming the TX_PTO bit of the transmitter settings register (the default upon reset). External terminations can be provided either by on-board resistors or by the input termination resistors of an HDMI/DVI receiver. If both the internal terminations are enabled and external terminations are present, set the output current level to 20 mA by programming the TX_OCL bit of the transmitter settings register (the default upon reset). If only external terminations are provided (if the internal terminations are disabled), set the output current level
Rev. 0 | Page 12 of 28
07050-026
DISABLE
IOUT
07050-025
AD8192
to 10 mA by programming the TX_OCL bit of the transmitter settings register. The high speed outputs must be disabled if there are no output termination resistors present in the system. The output equalizer (pre-emphasis) can be manually configured to provide one of four different levels of high frequency boost. The specific boost level is selected by programming the TX_PE bits of the transmitter settings register. No specific cable length is suggested for a particular pre-emphasis setting because cable performance varies widely among manufacturers. frequency response than that of the channel, thereby leading to improved high frequency energy, improved transition times, and improved eye opening on the far end of the channel. Using a pre-emphasis filter for compensating channel losses allows for longer cable runs with or without a receive equalizer on the far end of the channel. When there is no receive equalizer on the far end of the channel, the pre-emphasis filter should allow longer cable runs than is acceptable with no pre-emphasis. In the case of both a pre-emphasis filter on the near end and a receive equalizer on the far end of the channel, the allowable cable run should be longer than either compensation could achieve alone. The pulse response of a pre-emphasized waveform is shown in Figure 27. The output voltage levels and symbol descriptions are listed in Table 7 and Table 8, respectively.
PRE-EMPHASIS OFF VTTO VOCM VOSE-DC VL VH
SWITCHING MODE
The AD8192 is a 2:1 HDMI/DVI source switch. The user can select which high speed TMDS input is routed to the output by programming the HS_CH bit of the high speed modes register and which low speed DDC input/output is routed to the DDC common input/output by programming the AUX_CH bit of the auxiliary device register.
PRE-EMPHASIS
The pre-emphasized TMDS outputs precompensate the transmitted signal to account for losses in systems with long cable runs. These long cable runs selectively attenuate the high frequency energy of the signal, leading to degraded transition times and eye closure. Similar to a receive equalizer, the goal of the preemphasis filter is to boost the high frequency energy in the signal. However, unlike the receive equalizer, the pre-emphasis filter is applied before the channel, thus predistorting the transmitted signal to account for the loss of the channel. The series connection of the pre-emphasis filter and the channel results in a flatter Table 7. Output Voltage Levels
PE Setting 0 1 2 3 0 1 2 3 OCL Setting 0 0 0 0 1 1 1 1 Boost (dB) 0 2 4 6 0 2 4 6 IT (mA) 10 12.5 15 20 20 25 30 40 VOSE-DC (mV p-p) 250 250 250 250 500 500 500 500 VOSE-BOOST (mV p-p) 250 312.5 375 500 500 625 750 1000 VOCM (V) 3.175 3.144 3.133 3.050 3.050 2.988 2.925 2.8 DC-Coupled VH (V) VL (V) 3.3 3.050 3.3 2.988 3.3 2.925 3.3 2.8 3.3 2.8 3.3 2.675 3.3 2.550 3.3 2.3
PRE-EMPHASIS ON VTTO
VH VOSE-DC VOSE-BOOST VL VOCM
Figure 27. Pre-Emphasis Pulse Response
Table 8. Symbol Definitions
Symbol VOSE-DC VOSE-BOOST VOCM (DC-Coupled) VOCM (AC-Coupled) VH VL
1
Formula
IT
PE = 0
x 25
1
Definition Single-ended output voltage swing after settling Boosted single-ended output voltage swing Common-mode voltage when the output is dc-coupled Common-mode voltage when the output is ac-coupled High single-ended output voltage excursion Low single-ended output voltage excursion
IT x 25 1 I VTTO - T x 25 1 2 IT VTTO - x 50 2 VOCM + VOSE-BOOST/2 VOCM - VOSE-BOOST/2
The 25 resistance in the equation is the parallel combination of the on-chip 50 termination resistor and the external 50 termination resistor.
Rev. 0 | Page 13 of 28
07050-027
AD8192
AUXILIARY MULTIPLEXER
The auxiliary (low speed) lines provide switching and buffering for the DDC bus and buffering for the CEC line. The DDC buffers are bidirectional and fully support arbitration, clock synchronization, and other relevant features of a standard mode I2C bus. The CEC buffer is bidirectional and includes integrated on-chip pull-up resistors. The HPD lines going into the AD8192 are normally high impedance but are pulled low for greater than 100 ms when a channel switch occurs. The user has the option of slaving the auxiliary line switch select to the high speed switch select by programming the AUX_LK bit of the auxiliary device register. This causes the auxiliary input channel to switch automatically when the user programs the HS_CH bit of the high speed modes register. The unselected auxiliary inputs of the AD8192 are placed into a high impedance mode when the device is powered up and the DDC inputs of the AD8192 are high impedance when the device is powered off. This prevents contention on the DDC bus, enabling a design to include an EDID upstream of the AD8192.
INPUT/OUTPUT MAPPING CONTROL
The input/output mapping of the AD8192 is completely programmable. This allows a designer to integrate the AD8192 into virtually any application without requiring the use of vias on the TMDS traces in the PCB layout. The user can independently control the input/output mapping of the TMDS channels for both Source A and Source B by programming the A[3:0]_HS_MAP[0:1] bits of the Source A input/output mapping register and the B[3:0]_HS_MAP[0:1] bits of the Source B input/output mapping register, respectively. The user can independently control the polarity of the eight input channels by programming the A_SG and B_SG bits of the source sign select register. This allows a designer to invert the order of the p and n signals of a given TMDS pair inside the AD8192 instead of on the PCB.
DDC LOGIC LEVELS
The AD8192 supports the use of flexible (3.3 V, 5 V) logic levels on the DDC bus. The logic level for the DDC_A and DDC_B buses are set by the voltage on VREF_AB, and the logic level for the DDC_COM bus is set by the voltage on VREF_COM. For example, if the DDC_COM bus is using 5 V I2C, then the VREF_COM power supply pin should be connected to a +5 V power supply. If the DDC_AB buses are using 3.3 V I2C, then the VREF_AB power supply pin should be connected to a +3.3 V power supply.
Rev. 0 | Page 14 of 28
AD8192 SERIAL CONTROL INTERFACE
RESET
On initial power-up, or at any point during operation, the AD8192 register set can be restored to the default values by pulling the RESET pin to low according to the specification in Table 1. During normal operation, however, the RESET pin must be pulled up to 3.3 V. 7. 8. 9. Send the data (eight bits) to be written to the register whose address was set in Step 5. This transfer should be MSB first. Wait for the AD8192 to acknowledge the request. Do one of the following: a. Send a stop condition (while holding the I2C_SCL line high, pull the I2C_SDA line high) and release control of the bus to end the transaction (shown in Figure 28). b. Send a repeated start condition (while holding the I2C_SCL line high, pull the I2C_SDA line low) and continue with Step 2 in this procedure to perform another write. c. Send a repeated start condition (while holding the I2C_SCL line high, pull the I2C_SDA line low) and continue with Step 2 of the read procedure (in the Read Procedure section) to perform a read from another address. d. Send a repeated start condition (while holding the I2C_SCL line high, pull the I2C_SDA line low) and continue with Step 8 of the read procedure (in the Read Procedure section) to perform a read from the same address set in Step 5.
WRITE PROCEDURE
To write data to the AD8192 register set, an I2C master (such as a microcontroller) needs to send the appropriate control signals to the AD8192 slave device. The signals are controlled by the I2C master unless otherwise specified. For a diagram of the procedure, see Figure 28. The steps for a write procedure are as follows: 1. 2. Send a start condition (while holding the I2C_SCL line high, pull the I2C_SDA line low). Send the AD8192 part address (seven bits). The upper six bits of the AD8192 part address are the static value [100100] and the LSB is set by Input Pin I2C_ADDR. This transfer should be MSB first. Send the write indicator bit (0). Wait for the AD8192 to acknowledge the request. Send the register address (eight bits) to which data is to be written. This transfer should be MSB first. Wait for the AD8192 to acknowledge the request.
3. 4. 5. 6.
I2C_SCL R/W GENERAL CASE I2C_SDA START FIXED ADDR PART ADDR EXAMPLE I2C_SDA 1 2 3 4 5 6 7 8 9
07050-108
REGISTER ADDR ACK ACK
DATA ACK
STOP
Figure 28. I2C Write Procedure
Rev. 0 | Page 15 of 28
AD8192
I2C_SCL R/W GENERAL CASE I2C_SDA EXAMPLE I2C_SDA 1 2 3 4 5
2
R/W REGISTER ADDR SR ACK FIXED PART ADDR ADDR ACK DATA NACK STOP
START
FIXED PART ADDR
ADDR ACK
6
7
8
9 10 11
12
13
Figure 29. I C Read Procedure
READ PROCEDURE
To read data from the AD8192 register set, an I C master (such as a microcontroller) needs to send the appropriate control signals to the AD8192 slave device. The signals are controlled by the I2C master unless otherwise specified. For a diagram of the procedure, see Figure 29. The steps for a read procedure are as follows: 1. Send a start condition (while holding the I2C_SCL line high, pull the I2C_SDA line low). 2. Send the AD8192 part address (seven bits). The upper six bits of the AD8192 part address are the static value [100100], and the LSB is set by Input Pin I2C_ADDR. This transfer should be MSB first. 3. Send the write indicator bit (0). 4. Wait for the AD8192 to acknowledge the request. 5. Send the register address (eight bits) from which data is to be read. This transfer should be MSB first. 6. Wait for the AD8192 to acknowledge the request. 7. Send a repeated start condition (Sr) by holding the I2C_SCL line high and pulling the I2C_SDA line low. 8. Resend the AD8192 part address (seven bits) from Step 2. The upper six bits of the AD8192 part address compose the static value [100100]. The LSB is set by Input Pin I2C_ADDR. This transfer should be MSB first. 9. Send the read indicator bit (1). 10. Wait for the AD8192 to acknowledge the request. The AD8192 serially transfers the data (eight bits) held in the register indicated by the address set in Step 5. This data is sent MSB first. 11. Capture the data from the AD8192.
2
12. Do one of the following: a. Send a no acknowledge followed by a stop condition (while holding the I2C_SCL line high, pull the SDA line high) and release control of the bus to end the transaction (shown in Figure 29). b. Send a no acknowledge followed by a repeated start condition (while holding the I2C_SCL line high, pull the I2C_SDA line low) and continue with Step 2 of the write procedure (see the previous Write Procedure section) to perform a write. c. Send a no acknowledge followed by a repeated start condition (while holding the I2C_SCL line high, pull the I2C_SDA line low) and continue with Step 2 of this procedure to perform a read from another address. d. Send a no acknowledge followed by a repeated start condition (while holding the I2C_SCL line high, pull the I2C_SDA line low) and continue with Step 8 of this procedure to perform a read from the same address.
Rev. 0 | Page 16 of 28
07050-109
AD8192 CONFIGURATION REGISTERS
The serial interface configuration registers can be read and written using the I2C serial interface, Pin I2C_SDA, and Pin I2C_SCL. The least significant bit of the AD8192 I2C part address is set by tying the Pin I2C_ADDR to 3.3 V (I2C_ADDR = 1b) or 0 V (I2C_ADDR = 0b).
Table 9. Register Map
Name High Speed Device Modes Auxiliary Device Modes Receiver Settings Bit 7 Bit 6 High speed switch enable HS_EN Auxiliary switch enable AUX_EN Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 High speed source select Addr. Default 0x00 0x40
Auxiliary switch mode lock AUX_LK
Input Termination Control Receive Equalizer Transmitter Settings
RX_PT[7]
RX_PT[6]
RX_PT[5]
Input termination select RX_PT[4] RX_PT[3]
RX_PT[2]
RX_PT[1]
HS_CH Auxiliary 0x01 switch source select AUX_CH Input 0x10 termination control mode select RX_TO 0x11 RX_PT[0] 0x14 RX_EQ[0] Output current level select TX_OCL A_SG[0] 0x20
0xC0
0x01
0x00
RX_EQ[7]
RX_EQ[6]
RX_EQ[5]
Input equalization level select RX_EQ[4] RX_EQ[3] RX_EQ[2] Output pre-emphasis level select TX_PE[1]
0xFF 0x03
Source Sign Control Source A Input/ Output Mapping Source B Input/ Output Mapping
B_SG[3]
Source B input sign select B_SG[2] B_SG[1]
B_SG[0]
A_SG[3]
RX_EQ[1] Output termination on/off select TX_PE[0] TX_PTO Source A input sign select A_SG[2] A_SG[1]
0x80
0x00
A3_HS_MAP[1]
Sourch A high speed input/output mapping 0x81 A3_HS_MAP[0] A2_HS_MAP[1] A2_HS_MAP[0] A1_HS_MAP[1] A1_HS_MAP[0] A0_HS_MAP[1] A0_HS_MAP[0] Source B high speed input/output mapping 0x82 B3_HS_MAP[0] B2_HS_MAP[1] B2_HS_MAP[0] B1_HS_MAP[1] B1_HS_MAP[0] B0_HS_MAP[1] B0_HS_MAP[0]
0xE4
0xE4
B3_HS_MAP[1]
Rev. 0 | Page 17 of 28
AD8192
HIGH SPEED DEVICE MODES REGISTER
HS_EN: High Speed (TMDS) Switch Enable Bit
Table 10. HS_EN Description
HS_EN 0b 1b Description High speed channels off, low power/standby mode High speed channel on
INPUT TERMINATION CONTROL REGISTER
RX_PT[x]: High Speed (TMDS) Input Termination x, Select Bit
Table 16. RX_PT[x] Description
RX_PT[x] 0b 1b Description Input termination mode for TMDS Channel x is always disconnected Input termination for TMDS Channel x is always connected
HS_CH: High Speed (TMDS) Source Select Bit
Table 11. HS_CH Mapping
HS_CH 0b 1b O[3:0] A[3:0] B[3:0] Description High Speed Source A switched to output High Speed Source B switched to output
Table 17. RX_PT[x] Mapping
RX_PT[x] Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Corresponding Input TMDS Channel A0 A1 A2 A3 B3 B2 B1 B0
AUXILIARY DEVICE MODES REGISTER
AUX_LK: Auxiliary (Low Speed) Switch Mode Lock Bit
Table 12. AUX_LK Description
AUX_LK 0b 1b Description Auxiliary switch lock off, auxiliary source is switched independently of the high speed source Auxiliary switch lock on, auxiliary switch source select is slaved to the high speed switch source select bit
RECEIVE EQUALIZER REGISTER
RX_EQ[x]: High Speed (TMDS) Input x, Equalization Level Select Bit Table 18. RX_EQ[x] Description
RX_EQ[x] 0b 1b Description Low equalization (6 dB) High equalization (12 dB)
AUX_EN: Auxiliary (Low Speed) Switch Enable Bit
Table 13. AUX_EN Description
AUX_EN 0b 1b Description Auxiliary switch off, no low speed input/output to low speed common input/output connection Auxiliary switch on
Table 19. RX_EQ[x] Mapping
RX_EQ[x] Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Corresponding Input TMDS Channel A0 A1 A2 A3 B3 B2 B1 B0
AUX_CH: Auxiliary (Low Speed) Switch Source Select Bit
Table 14. AUX_CH Mapping
AUX_CH 0b 1b AUX_COM[3:0] AUX_A[3:0] AUX_B[3:0] Description Auxiliary Source A switched to output Auxiliary Source B switched to output
RECEIVER SETTINGS REGISTER
RX_TO: High Speed (TMDS) Input Termination Mode Control Select Bit
Table 15. RX_TO Description
RX_TO 0b Description Input termination mode is manual, individual terminations can be enabled/disabled according to settings in the input termination pulse register Input termination for TMDS Channel x is always connected
1b
Rev. 0 | Page 18 of 28
AD8192
TRANSMITTER SETTINGS REGISTER
TX_PE[x]: High Speed (TMDS) Output Pre-Emphasis Level Select Bus (For All TMDS Channels)
Table 20. TX_PE[x] Description
TX_PE[x] 00b 01b 10b 11b Description No pre-emphasis (0 dB) Low pre-emphasis (2 dB) Medium pre-emphasis (4 dB) High pre-emphasis (6 dB)
B_SG[x]: High Speed (TMDS) Input B, Channel x Sign Select Bits
These bits define the input/input complement polarity of the Channel x.
Table 25. B_SG[x] Description
B_SG[x] 0b 1b Description Channel sign is positive Channel sign is inverted
Table 26. B_SG[x] Mapping
B_SG[x] 0b 1b OP[x] IP_B[x] IN_B[x] ON[x] IN_B[x] IP_B[x]
TX_PTO: High Speed (TMDS) Output Termination On/Off Select Bit (For All Channels)
Table 21. TX_PTO Description
TX_PTO 0b 1b Description Output termination off Output termination on
SOURCE A INPUT/OUTPUT MAPPING REGISTER
A[x]_HS_MAP[1:0]: High Speed (TMDS) Input A, Output Channel x, Select Bits
These bits define the input/output mapping of the high speed channels when Source A is selected. Table 27. A[x]_HS_MAP[1:0] Mapping
A[x]_HS_MAP[1:0] 00b 01b 10b 11b O[x] A0 A1 A2 A3
TX_OCL: High Speed (TMDS) Output Current Level Select Bit (For All Channels)
Table 22. TX_OCL Description
TX_OCL 0b 1b Description Output current set to 10 mA Output current set to 20 mA
SOURCE SIGN CONTROL REGISTER
A_SG[x]: High Speed (TMDS) Input A, Channel x Sign Select Bits
Defines the input/input complement polarity of the Channel x. Table 23. A_SG[x] Description
A_SG[x] 0b 1b Description Channel sign is positive Channel sign is inverted
SOURCE B INPUT/OUTPUT MAPPING REGISTER
B[x]_HS_MAP[1:0]: High speed (TMDS) Input B, Output Channel x, Select Bits
These bits define the input/output mapping of the high speed channels when Source B is selected. Table 28. B[x]_HS_MAP[1:0] Mapping
B[x]_HS_MAP[1:0] 00b 01b 10b 11b O[x] B0 B1 B2 B3
Table 24. A_SG[x] Mapping
A_SG[x] 0b 1b OP[x] IP_A[x] IN_A[x] ON[x] IN_A[x] IP_A[x]
Rev. 0 | Page 19 of 28
AD8192 APPLICATIONS INFORMATION
+5V +3.3V
TMDS D2+ D2- D1+ D1- D0+ D0- CLK+ CLK- ESD PROT. (OPTIONAL) IPA3 INA3 IPA2 INA2 IPA1 INA1 IPA0 INA0 2k AMUXVCC VREF_AB AVCC, DVCC VTTI, VTTO
AD8192
47 1k k 47 k HPD_A SCL_A SDA_A OUTP3 OUTN3 OUTP2 OUTN2 OUTP1 OUTN1 OUTP0 OUTN0 VREF_COM CEC_I/O SCL_COM SDA_COM TMDS D2+ D2- D1+ D1- D0+ D0- CLK+ CLK- 2k HDMI RECEIVER
+5V HPD DDC_SCL DDC_SDA CEC
0.01uF
EDID EEPROM
+3.3V OR +5V 2k
TMDS D2+ D2- D1+ D1- D0+ D0- CLK+ CLK- IPB3 INB3 IPB2 INB2 IPB1 INB1 IPB0 INB0 2k +3.3V 1k CEC_O/I I2C_SCL I2C_SDA I2C_ADDR 2k 2k
ESD PROT. (OPTIONAL)
MCU
+5V HPD DDC_SCL DDC_SDA CEC
47 1k k
47 k
HPD_B SCL_B SDA_B
AVEE, DVEE
0.01uF
EDID EEPROM
07050-030
Figure 30. Typical Simplified Schematic
The AD8192 is an HDMI/DVI switch featuring equalized TMDS inputs, pre-emphasized TMDS outputs, and buffered auxiliary signals. It is intended for use as a 2:1 switch in systems with long cable runs on both the input and/or the output, and is fully HDMI 1.3a transmit and receive compliant.
PINOUT
By default, the AD8192 is designed to have an HDMI/DVI receiver pinout at its input and a transmitter pinout at its output. However, the input/output mapping of the AD8192 is completely programmable via the serial control interface. This allows a designer to integrate the AD8192 into virtually any application without requiring the use of vias on the TMDS traces in the PCB layout. In addition to 12 dB of input equalization, the AD8192 provides up to 6 dB of output pre-emphasis that boosts the output TMDS
signals and allows the AD8192 to precompensate when driving long PCB traces or output cables. The net effect of the input equalization and output pre-emphasis of the AD8192 is that the AD8192 can compensate for the signal degradation of both input and output cables; it acts to reopen a closed input data eye and transmit a full swing HDMI signal to an end receiver. The AD8192 also provides a distinct advantage in receive-type applications because it is a fully buffered HDMI/DVI switch; the AD8192 fully buffers and electrically decouples the outputs from the inputs for both the TMDS and the auxiliary lines. Therefore, the effects of any vias placed on the output signal lines are not seen at the input of the AD8192. The programmable output terminations also improve signal quality at the output of the AD8192. Thus, the PCB designer has significantly increased flexibility in the placement and routing of the output signal path with the AD8192 over other solutions.
Rev. 0 | Page 20 of 28
AD8192
CABLE LENGTHS AND EQUALIZATION
The AD8192 offers two levels of programmable equalization for the high speed inputs: 6 dB and 12 dB. The equalizer of the AD8192 supports video data rates of up to 2.25 Gbps and can equalize more than 20 meters of 24 AWG HDMI cable at 2.25 Gbps, which corresponds to the video format 1080p with 12-bit deep color. The length of cable that can be used in a typical HDMI/DVI application depends on a large number of factors including * Cable quality: the quality of the cable in terms of conductor wire gauge and shielding. Thicker conductors have lower signal degradation per unit length. Data rate: the data rate being sent over the cable. The signal degradation of HDMI cables increases with data rate. Edge rates: the edge rates of the source input. Slower input edges result in more significant data eye closure at the end of a cable. Receiver sensitivity: the sensitivity of the terminating receiver.
HDTV SET
MAIN PCB
AD8192
HDMI RX
CABLE
* *
Figure 31. AD8192 as a Front Panel Buffer for an HDTV
*
HDMI SWITCHER
In home theatre applications where more HDMI inputs are needed, a multiple input HDMI switcher can be used to extend the number of available HDMI inputs. This switch can be contained within an audio/video receiver (AVR) or as a standalone unit. The AD8192 can be cascaded to create larger arrays as shown in Figure 32.
As such, specific cable types and lengths are not recommended for use with a particular equalizer setting. In nearly all applications, the AD8192 equalization level can be set to high, or 12 dB, for all input cable configurations at all data rates, without degrading the signal integrity.
TMDS OUTPUT RISE/FALL TIMES
The TMDS outputs of the AD8192 are designed for optimal performance even when external components are connected such as external ESD protection, common-mode filters, and the HDMI connector. In applications where the output of the AD8192 is connected to an HDMI output connector, additional ESD protection is recommended. The capacitance of the additional ESD protection circuits for the TMDS outputs should be as low as possible. In a typical application, the output rise/fall times are compliant with the HDMI 1.3a specification at the output of the HDMI connector.
EQ
AD8192
EQ EQ
AD8192
EQ EQ
AD8192
07050-132
FRONT PANEL BUFFER FOR ADVANCED TV
A front panel input provides easy access to an HDMI connector for connecting an HD camcorder or video game console to an HDTV. In designs where the main PCB is not near the side or front of the HDTV, a front panel buffer must be connected to the main board by a cable. The AD8192 enables the implementation of a front or side panel HDMI input for an HDTV by buffering the HDMI signals and compensating for the cable interconnect to the main board.
EQ
Figure 32. AD8192 Cascaded as a 4:1 HDMI Switcher
CASCADING MULTIPLE DEVICES
Unlike traditional I2C bidirectional buffers, the DDC/CEC buffers in the AD8192 can be cascaded to create larger arrays such as those shown in Figure 32. The TMDS signals can also be cascaded, although it is important to use caution because cascading high gain equalizers can increase the output jitter beyond acceptable limits. In such cases, set the programmable equalizer in the AD8192 to low (6 dB).
Rev. 0 | Page 21 of 28
07050-031
AD8192
PCB LAYOUT GUIDELINES
The AD8192 switches two distinctly different types of signals, both of which are required for HDMI and DVI video. These signal groups require different treatment when laying out a PCB. The first group of signals carries the AV data. HDMI/DVI video signals are differential, unidirectional, and high speed (up to 2.25 Gbps). The channels that carry the video data must be controlled impedance, terminated at the receiver, and capable of operating up to at least 2.25 Gbps. It is especially important to note that the differential traces that carry the TMDS signals should be designed with a controlled differential impedance of 100 . The AD8192 provides single-ended 50 terminations on-chip for both its inputs and outputs, and both the input and output terminations can be enabled or disabled through the serial interface. Transmitter termination is not fully specified by the HDMI standard but its inclusion improves the overall system signal integrity. The AV data carried on these high speed channels is encoded by a technique called transition minimized differential signaling (TMDS) and in the case of HDMI, is also encrypted according to the high bandwidth digital copy protection (HDCP) standard. The second group of signals consists of low speed auxiliary control signals used for communication between a source and a sink. Depending upon the application, these signals can include the DDC bus (this is an I2C bus used to send EDID information and HDCP encryption keys between the source and the sink), the CEC line, and the HPD line. These auxiliary signals are bidirectional, low speed, and transferred over a single-ended transmission line that does not need to have controlled impedance. The primary concern with laying out the auxiliary lines is ensuring that they conform to the I2C bus standard and do not have excessive capacitive loading. speed signals should be routed on a PCB in accordance with the same RF layout guidelines.
Layout for the TMDS Signals
The TMDS differential pairs can be either microstrip traces (routed on the outer layer of a board) or stripline traces (routed on an internal layer of the board). If microstrip traces are used, there should be a continuous reference plane on the PCB layer directly below the traces. If stripline traces are used, they must be sandwiched between two continuous reference planes in the PCB stack up. Additionally, the p and n of each differential pair must have a controlled differential impedance of 100 . The characteristic impedance of a differential pair is a function of several variables including the trace width, the distance separating the two traces, the spacing between the traces and the reference plane, and the dielectric constant of the PCB binder material. Interlayer vias introduce impedance discontinuities that can cause reflections and jitter on the signal path; therefore, it is preferable to route the TMDS lines exclusively on one layer of the board, particularly for the input traces. Additionally, to prevent unwanted signal coupling and interference, route the TMDS signals away from other signals and noise sources on the PCB. Both traces of a given differential pair must be equal in length to minimize intrapair skew. Maintaining the physical symmetry of a differential pair is integral to ensuring its signal integrity; excessive intrapair skew can introduce jitter through duty cycle distortion (DCD). The p and n of a given differential pair should always be routed together to establish the required 100 differential impedance. Leave enough space between the differential pairs of a given group to prevent the n of one pair from coupling to the p of another pair. For example, one technique is to make the interpair distance 4 to 10 times wider than the intrapair spacing. Any one group of four TMDS traces (either Input A, Input B, or the outputs) should have closely matched trace lengths to minimize interpair skew. Severe interpair skew can cause the data on the four different channels of a group to arrive out of alignment with one another. A good practice is to match the trace lengths for a given group of four channels to within 0.05 inches on FR4 material. Minimizing intrapair and interpair skew becomes increasingly important as data rates increase. Any introduced skew constitutes a correspondingly larger fraction of a bit period at higher data rates. Though the AD8192 features input equalization and output preemphasis, minimizing the length of the TMDS traces is needed to reduce overall system signal degradation. Commonly used PCB material, such as FR4, is lossy at high frequencies, therefore, long traces on the circuit board increase signal attenuation, resulting in decreased signal swing and increased jitter through intersymbol interference (ISI).
TMDS Signals
In the HDMI/DVI standard, four differential pairs carry the TMDS signals. In DVI, three of these pairs are dedicated to carrying RGB video and sync data. For HDMI, audio data interleaves with the video data; the DVI standard does not incorporate audio information. The fourth high speed differential pair is used for the AV data-word clock and runs at one-tenth the speed of the TMDS data channels. The four high speed channels of each input of the AD8192 are identical. No concession was made to lower the bandwidth of the fourth channel for the pixel clock; therefore, any channel can be used for any TMDS signal. An external 2 k pull-down resistor on the TMDS CLKN signal is recommended for improved noise immunity as shown in Figure 30. The AD8192 buffers the TMDS signals and the input traces can be considered electrically independent of the output traces. In most applications, the quality of the signal on the input TMDS traces is more sensitive to the PCB layout. Regardless of the data being carried on a specific TMDS channel, or whether the TMDS line is at the input or the output of the AD8192, all four high
Rev. 0 | Page 22 of 28
AD8192
Controlling the Characteristic Impedance of a TMDS Differential Pair
The characteristic impedance of a differential pair depends on a number of variables including the trace width, the distance between the two traces, the height of the dielectric material between the trace and the reference plane below it, and the dielectric constant of the PCB binder material. To a lesser extent, the characteristic impedance also depends upon the trace thickness and the presence of solder mask. There are many combinations that can produce the correct characteristic impedance. Generally, working with the PCB fabricator is required to obtain a set of parameters to produce the desired results. One consideration is how to guarantee a differential pair with a differential impedance of 100 over the entire length of the trace. One technique to accomplish this is to change the width of the traces in a differential pair based on how closely one trace is coupled to the other. When the two traces of a differential pair are close and strongly coupled, they should have a width that produces a100 differential impedance. When the traces split apart to go into a connector, for example, and are no longer so strongly coupled, the width of the traces needs to be increased to yield a differential impedance of 100 in the new configuration.
TMDS Terminations
The AD8192 provides internal 50 single-ended terminations for all of its high speed inputs and outputs. It is not necessary to include external termination resistors for the TMDS differential pairs on the PCB. The output termination resistors of the AD8192 back terminate the output TMDS transmission lines. These back terminations act to absorb reflections from impedance discontinuities on the output traces, improving the signal integrity of the output traces and adding flexibility to how the output traces can be routed. For example, interlayer vias can be used to route the AD8192 TMDS outputs on multiple layers of the PCB without severely degrading the quality of the output signal.
Auxiliary Control Signals
There are four single-ended control signals associated with each source or sink in an HDMI/DVI application. These are hot plug detect (HPD), consumer electronics control (CEC), and two display data channel (DDC) lines. The two signals on the DDC bus are SDA and SCL (serial data and serial clock, respectively). The DDC and CEC signals are buffered and switched through the AD8192, and the HPD signal is pulsed low by the AD8192. These signals do not need to be routed with the same strict considerations as the high speed TMDS signals. In general, it is sufficient to route each auxiliary signal as a single-ended trace. These signals are not sensitive to impedance discontinuities, do not require a reference plane, and can be routed on multiple layers of the PCB. However, it is best to follow strict layout practices whenever possible to prevent the PCB design from affecting the overall application. The specific routing of the HPD, CEC, and DDC lines depends upon the application in which the AD8192 is being used. For example, the maximum speed of signals present on the auxiliary lines are 100 kHz I2C data on the DDC lines, therefore, any layout that enables 100 kHz I2C to be passed over the DDC bus should suffice. The HDMI 1.3a specification, however, places a strict 50 pF limit on the amount of capacitance that can be measured on either SDA or SCL at the HDMI input connector. This 50 pF limit includes the HDMI connector, the PCB, and whatever capacitance is seen at the input of the AD8192, or an equivalent receiver. There is a similar limit of 150 pF of input capacitance for the CEC line. The benefit of the AD8192 is that it buffers these lines, isolating the output capacitance so that only the capacitance at the input side contributes to the specified limit. Good board design is still required, however. The parasitic capacitance of traces on a PCB increases with trace length. To help ensure that a design satisfies the HDMI specification, the length of the CEC and DDC lines on the PCB should be made as short as possible. Additionally, if there is a reference plane in the layer adjacent to the auxiliary traces in the PCB stackup, relieving or clearing out this reference plane immediately under the auxiliary traces significantly decreases
Ground Current Return
In some applications, it can be necessary to invert the output pin order of the AD8192. This requires a designer to route the TMDS traces on multiple layers of the PCB. When routing differential pairs on multiple layers, it is necessary to also reroute the corresponding reference plane to provide one continuous ground current return path for the differential signals. Standard plated through-hole vias are acceptable for both the TMDS traces and the reference plane. An example of this is illustrated in Figure 33.
THROUGH-HOLE VIAS
SILKSCREEN LAYER 1: SIGNAL (MICROSTRIP) PCB DIELECTRIC LAYER 2: GND (REFERENCE PLANE) PCB DIELECTRIC LAYER 3: PWR (REFERENCE PLANE) PCB DIELECTRIC LAYER 4: SIGNAL (MICROSTRIP) SILKSCREEN KEEP REFERENCE PLANE ADJACENT TO SIGNAL ON ALL LAYERS TO PROVIDE CONTINUOUS GROUND CURRENT RETURN PATH.
Figure 33. Example Routing of Reference Plane
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07050-032
AD8192
the amount of parasitic trace capacitance. An example of the board stackup is shown in Figure 34.
3W W 3W
SILKSCREEN LAYER 1: SIGNAL (MICROSTRIP) PCB DIELECTRIC LAYER 2: GND (REFERENCE PLANE) PCB DIELECTRIC LAYER 3: PWR (REFERENCE PLANE) PCB DIELECTRIC LAYER 4: SIGNAL (MICROSTRIP) SILKSCREEN REFERENCE LAYER RELIEVED UNDERNEATH MICROSTRIP
07050-033
The AVCC/AVEE (3.3 V) and DVCC/DVEE (3.3 V) supplies power the core of the AD8192. The VTTI/AVEE supply (3.3 V) powers the input termination. Similarly, the VTTO/AVEE supply (3.3 V) powers the output termination. The AMUXVCC/ DVEE supply (3.3 V to 5 V) powers the auxiliary multiplexer core. The VREF_COM and VREF_AB supplies determine the logic levels on the corresponding DDC buses. For example, if the DDC_COM bus is using 5 V I2C, then VREF_COM should be connected to +5 V relative to DVEE. If the DDC_AB buses are using 3.3 V I2C, then VREF_AB should be connected to +5 V relative to DVEE. In a typical application, connect all pins labeled AVEE or DVEE directly to ground. Likewise, connect all pins labeled AVCC, DVCC, VTTI, or VTTO to 3.3 V, and tie Pin AMUXVCC to 5 V. VREF_AB and VREF_COM can be tied to either 3.3 V or 5 V, depending on the application. The supplies can also be powered individually, but care must be taken to ensure that each stage of the AD8192 is powered correctly.
Figure 34. Example Board Stackup
Power Supply Bypassing
The AD8192 requires minimal supply bypassing. When powering the supplies individually, place a 0.01 F capacitor between each 3.3 V supply pin (AVCC, DVCC, VTTI, and VTTO) and ground, and place a 0.1 F capacitor between each additional supply pin (AMUXVCC, VREF_AB, and VREF_COM) and ground to filter out supply noise. Generally, place bypass capacitors near the power pins and connect them directly to the relevant supplies (without long intervening traces). For example, to improve the parasitic inductance of the power supply decoupling capacitors, minimize the trace length between capacitor landing pads and the vias. In applications where the AD8192 is powered by a single 3.3 V supply, it is recommended to use two reference supply planes and bypass the 3.3 V reference plane to the ground reference plane with one 220 pF, one 1000 pF, two 0.01 F, and one 4.7 F capacitors. If the AMUXVCC, VREF_AB, and VREF_COM connections are all powered by a single 5 V supply, it is sufficient to use a single 0.1 F to bypass all three connections. The capacitors should via down directly to the supply planes and be placed within a few centimeters of the AD8192.
HPD is a dc signal presented by a sink to a source to indicate that the source EDID is available for reading. The placement of this signal is not critical, but it should be routed as directly as possible. When the AD8192 is powered up, the DDC/CEC inputs of the selected channel are actively buffered and routed to the outputs, and the unselected auxiliary inputs are high impedance. When the AD8192 is powered off, all DDC/CEC inputs are placed in a high impedance state. This prevents contention on the DDC bus, enabling a design to include an EDID in front of the AD8192.
Power Supplies
The AD8192 has five separate power supplies referenced to two separate grounds. The supply/ground pairs are * * * * * * * AVCC/AVEE VTTI/AVEE VTTO/AVEE DVCC/DVEE AMUXVCC/DVEE VREF_AB/DVEE VREF_COM/DVEE
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AD8192 OUTLINE DIMENSIONS
8.00 BSC SQ 0.60 MAX 0.60 MAX
43 42 PIN 1 INDICATOR
0.30 0.23 0.18
56 1
PIN 1 INDICATOR
TOP VIEW
7.75 BSC SQ
*EXPOSED PAD (BOTTOM VIEW)
4.95 4.80 SQ 4.65
0.50 0.40 0.30
29 28
14 15
0.30 MIN 1.00 0.85 0.80 12 MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 6.50 REF
SEATING PLANE
0.50 BSC
COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2 *NOTE: THE AD8192 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF THE DEVICE OVER THE FULL HDMI/DVI TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF THE PACKAGE AND ELECTRICALLY CONNECTED TO AVEE. IT IS RECOMMENDED THAT NO PCB SIGNAL TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE SLUG. ATTACHING THE SLUG TO AN AVEE PLANE REDUCES THE JUNCTION TEMPERATURE OF THE DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
Figure 35. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 8 mm x 8 mm Body, Very Thin Quad (CP-56-3) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8192ACPZ1 AD8192ACPZ-RL71 AD8192-EVALZ1
1
Temperature Range -40C to +85C -40C to +85C
Package Description 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Reel 7 Evaluation Board
Package Option CP-56-3 CP-56-3
033108-A
Ordering Quantity 750
Z = RoHS Compliant Part.
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AD8192 NOTES
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AD8192 NOTES
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AD8192 NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07050-0-5/08(0)
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